Zvonimir Z. Bandić is the vice president of the RISC-V CPU group in Cadence Design Systems. Prior to Cadence, Zvonimir held number of senior R&D roles in IBM, Hitachi, HGST and Western Digital Corporation, all in San Jose, California. He received his bachelor’s in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his master’s (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focused on delivering broad RISC-V CPU roadmap for Cadence, covering range from ultra-small low power cores to Linux/Android capable RISC-V CPU IP. In addition to RISC-V CPU technologies, Zvonimir has broad experience in innovation on system on chip (SoC) architectures for emerging non-volatile memory (PCM, ReRAM, MRAM) controllers, traditional NAND controllers for SSD applications, machine learning hardware acceleration (including first WDC neural network inferencing accelerator device), distributed computing and accelerators for distributed computing, in-memory compute, RDMA networking and NVMe over fabrics and Security and Root of Trust IP design. Since 2020, he has been collaborating with Perimeter Institute of Theoretical Physics on Quantum Error Correction Codes for Quantum Computing, and got involved as a mentor in CDL-Toronto. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers. Over the years, Zvonimir served as chairman of OpenCAPI, chairman and founder of CHIPS Alliance, board of directors member of RISC-V International and OpenTitan, and many other open architecture and standards organizations.